Welcome to the Bit Accurate Modelling Website.

This website is a personal project that began as a spinoff from postgraduate work, and was further developed as part of a project with the Signal Processing Microelectronics group at the University of Newcastle in Australia. As a contribution to the research community, this website has been created to make this information and software freely available.

These projects are focussed on providing software solutions to assist the mapping of algorithmic solutions to actual implementations in hardware devices. This includes bit accurate modelling of numerical systems in limited precision, analysis of those simulations, and generation of test data for verification with the hardware implementations in ASICs and FPGAs.

Note : This website is effectively in legacy mode. The downloads had to be removed due to uncertainties over rights to place them here (Although I wrote it, doesn't mean I get to call the shots on it...). I hope to rewrite and revive this project eventually, but that may be some time away.

What is Bit Accurate Modelling?


Bit accurate modelling is an essential step in the transitioning of high level algorithms to implementation in custom silicon devices, such as Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs).

While an algorithm researcher may have an idea that performs well on a numerical package such as MATLAB, that runs with the double or single precision floating point format used by the computer's CPU. For implementation in a power efficient silicon device, this level of precision may be infeasible, and so a limited precision model of the algorithm is required. An initial limited precision model may not closely mimic performance of any particular hardware, but instead provides an estimate of how well the algorithm may perform under those conditions.


In order to confidently study the effects of limited precision on the algorithm performance, it is desirable for that model to match the behaviour of the proposed hardware exactly. That is, a "bit accurate" model - one where every bit of the software model output exactly matches the corresponding bits of the proposed hardware. Such a model can then be reused during the development cycle for debugging the hardware, by generating test vectors for harware verification, and also by inputting real-word inputs into the software model for analysis.

Most labs that do this sort of work may already have their own in-house solutions and, indeed, a number of commercial and open source options are also available. However, these are often targeted to a particular style of implementation, or are too inflexible to be able to customise to a particular project. Quite often, time is wasted rewriting the same type of tools over and over again.

Therefore, the motivation behind the c4Hardware and c4HDL projects is to provide a highly flexible framework that can achieve all of the above, and be adapted to suit the needs of a particular project. The individual components of this project are described below.

Projects

 

c4Hardware

c4Hardware is a highly flexible library of C++ classes for the emulation of hardware implementations of algorithms. It provides a high level interface to matrix, vector, and scalar operations to allow rapid application development without requiring knowledge of the underlying operations. Futhermore, it allows custom data types to be plugged-in with little change to the high level application. This allows bit-accurate modelling and analysis of algorithms under various limited precision numerical representations. c4Hardware programs may be either standalone execuatables, or coded as MEX functions for interfacing with MATLAB.

 

c4HDL

c4HDL is a library of C++ classes that provides bit-accurate modelling of integer, floating point, and fixed point data types, for matching with HDL code. Key points include :
  • Allows modelling from very small to very large numerical precision
  • Models can be directly used for generating testbench data to verify the operation of HDL models of the algorithm.
  • Contains and generates matching C++ and VHDL models of some arithmetic hardware components
While designed as a plug-in for c4Hardware, this library may also be used as a standalone item.